Configuration and control registers for the CDC-ACM FIFOs.
| USB_SERIAL_JTAG_WR_DONE | Set this bit to indicate writing byte data to UART Tx FIFO is done. |
| USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE | 1’b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host. |
| USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL | 1’b1: Indicate there is data in UART Rx FIFO. |